Random defects occurring during the manufacturing of an integrated circuit with embedded memory blocks can render certain non-redundant elements of an integrated circuit memory device, such as a memory column, defective. For example, particle contamination during the manufacturing process may cause broken or shorted out columns and bit defects.
Redundant elements in an integrated circuit memory device, such as redundant columns, are used to compensate for these random defects. Initial testing of an integrated circuit memory occurs after the manufacturing process. During initial testing of an integrated circuit memory device, defective elements are replaced by non-defective elements referred to as redundant elements. Thus, redundant columns may be used in a scheme to replace defective non-redundant columns, discovered during initial testing of the integrated circuit memory device. The use of redundant elements is important in increasing the overall yield of an integrated circuit memory device.
FIG. 1 illustrates a block diagram of a prior art external test solution to test an embedded memory possessing a redundancy structure used in a System on a Chip (SoC). As more memory is used on a SoC 102, the yield of the memories decreases. SoC 102 integrate on-chip memory 104 with processors and other similar components all on the same chip to decrease cost and increase performance. Redundancy techniques include adding extra memory rows and memory columns that can be substituted for defective elements. This current external test solution 106 necessitates a costly investment in external test equipment to find and fix defects. The current external test may cost companies millions of dollars.
Also, four equipment insertions may be required when testing SoC memory 104. First, the external memory tester 108 tests the memory to find defective components on the SoC 102 die. The external memory tester 108 imports the failure results in order to perform redundancy analysis and allocation. The external memory tester 108 sends the repair signature, or in other words the information on how to allocate the repair elements for any defects, to the laser repair equipment 110. Second, the laser repair equipment 110 blows the fuses on the SoC 102 wafer that enable the redundant rows and memory columns to be substituted for the defective memory cells. Third, the memory tester 108 re-tests memory on the SoC 102 to ensure that the repairs were made properly. Last, the logic tester 112 analyzes the remaining non-memory components of the SoC 102.
The external test solution 106 is expensive, time-consuming, may not achieve a dramatic increase in yield, and in the future it may not be a feasible solution for SoC testing. The memory tester 108 assumes that the memories 104 used in a SoC 102 are readily accessible directly from the I/O pins of the chip. A designer must carefully route each embedded memory 104 to enable pin access. As more embedded memories 104 are physically located onto a chip containing the entire system, more design time is required to route the embedded memories 104 and establish the pin connections. Meanwhile, the die size may increase from the extra routing, and chip packages may enlarge accordingly. The physical size and spacing requirements of SoC 102 dies may not accommodate the extra space need to test the memories. Also, memory tester 108 may not be able to test the memories at the speed of the chip.
Typically, a device external to the processor applies, via parallel or serial interface, an instruction sequence commonly referred to as vectors. The vectors drive a test and repair processor located on the system on a chip. The device external to the processor makes multiple attempts and handshaking operations with the processor to perform all of the test and repair operations on the memory. Usually, extra logic may be included in the system design to coordinate and drive the test and repair processor to perform these operations. Further, the design of the extra logic may become more complicated if the logic has the intelligence to determine whether it wants all of the test and repair operations performed or just a portion of those operations performed. Thus, extra time and expense may be added into a system on a chip design to accommodate the extra logic.